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| BCM8128 (R) MULTI-RATE 10-GBPS SONET/SDH/10GE/FEC MUX FEATURES * 10-Gigabit MSA (Multi-Source Agreement) compliant * Fully integrated Clock Multiplication Unit (CMU) supports multiple rates: OC-192, 10GE, 10GFC and its FEC rates SUMMARY OF BENEFITS * Compliant with Optical Internetworking Forum (OIF), * 16:1 multiplexer with LVDS data input * Configurable divide by 16 or 32 clock modes * Configurable LVDS input clock-to-data bus timing skew control * On-chip 16 x 10 FIFO eliminates system timing issues * Serial data polarity invert Telcordia, ITU-T, ANSI, and IEEE 802.3ae industry standards. * Reduces design cycle and time to market. * High level of integration allows for higher port density solutions. * Uses the most effective silicon economy of scale for CMOSbased devices. * Low-power consumption eliminates the need for external cooling sources. * Bit order reversal * Low Jitter 10 Gigabit Output Clock for retiming lased Tx clock output * Lock detect * Core power supply: 1.8V APPLICATIONS * * * * * * * * OC-192/STM-64/10GE transmission equipment SONET/SDH optical modules ADD/DROP multiplexers Digital cross-connects ATM switch backbones SONET test equipment Terabit routers Edge routers * I/O power supply: CML at 1.8V, LVDS and CMOS at 1.8V or 3.3V * Power consumption: 450 mW * Standard CMOS fabrication process * 127-pin BGA package BCM8128 Functional Block Diagram Network Interface Processor BCM8128 ORX ORX BCM8129 10-Gb Serial Data BCM8129 ORX ORX BCM8128 XSBI (16 Bit) Parallel Data XSBI (16 Bit) Parallel Data Network Interface Processor OVERVIEW TxRESET FIFO Control TxFIFOERR RB_SKEW TxPICLKSEL TxSKEWSEL0/1 Divide by 16 or 32 LVDS Clock TxPICLKP TxPICLKN POLSEL LSBSEL Skew Control Write Pointer INPUT REGISTER TxDIN0P TxDIN0N 16 x 10 FIFO 16:1 MUX Output Retime TSDP TSDN TSCLKP TSCLKN CML 10G Serial Data Output TxDIN15P TxDIN15N TxRATESEL0 TxRATESEL1 CML 10G Clock Output Read Pointer TxPCLKP Divide by 16 Clock Output Divide by 16 or 64 LVPECL Reference Clock TxREFCLKP 10GHz CMU TxREFCLKN Divide-by-16 TxPCLKN TxLOCKERR PDCLNPLL SYSCLKP SYSCLKN TxREFSEL VCPCLNPLL TxMCLKP Phase Detector Charge Pump Divide-by-4 TxMCLKN Selectable divide by 16 or 64 Clock Output The BCM8128 is a fully integrated MSA-compliant quad-rate SONET/ SDH/10GE transmitter operating at OC-192 (9.953 Gbps), 10GE (10.3125 Gbps), 10GFC (10.513 Gbps), and FEC (Forward Error Correction) data rates (10.664/10.709, 11.096, or 11.31 Gbps) with serializer and Clock Multiplication Unit (CMU). The low-jitter LVDS interface and onboard low-jitter PLL exceed Optical Internetworking Forum (OIF), IEEE 802.3ae, Telcordia, ANSI, and ITU-T jitter standards. The BCM8128 reference clock input frequency is user-selectable to the line rate divided by either 16 or 64. The two reference clock outputs can be squelched under user control. The BCM8128 provides skew control between the LVDS transmit parallel input clock and data to accommodate difficult timing variances. A 10-word FIFO decouples the parallel input timing domain from the serial output timing domain. The BCM8128 provides a CML serial output clock to retime the data at the optical interface. The BCM8128 can be powered with a single 1.8V supply or dual 1.8/ 3.3V supply without any special power supply sequencing requirements. The BCM8128 comes in a 11 x 11 mm, 127-pin BGA package. Broadcom(R), the pulse logo, and Connecting everything(R) are trademarks of Broadcom Corporation and/ or its subsidiaries in the United States and certain other countries. All other trademarks mentioned are the property of their respective owners. (R) BROADCOM CORPORATION 16215 Alton Parkway, P.O. Box 57013 Irvine, California 92619-7013 (c) 2004 by BROADCOM CORPORATION. All rights reserved. 8128-PB02-R 04/13/04 Phone: 949-450-8700 Fax: 949-450-8710 E-mail: info@broadcom.com Web: www.broadcom.com |
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